A lateral power switch/transistor can be fabricated on a silicon wafer in a customized, high speed, laterally diffused metal oxide semiconductor (“LDMOS”) process. The lateral power switch is formed of a large number of cells with routing in and out of device terminals allowed on the top side of a wafer. Unlike traditional vertical- and trench-style devices, back-side routing is not typically employed. In addition, with the use of deep sub-micron lithography, the pitch (or half-pitch) of a cell drops below five microns (micrometers (“μm”)), which makes source and drain metallizations tighter with less available space to couple to upper-level metal contacts. The upper-level metal contacts are routed to an external package pin located at a periphery of a semiconductor package. This difficulty translates into two adverse challenges.
A first challenge is decreased metal widths, which leads to increased resistance between high-current drain and source terminals of the switch and external package pins. A second challenge is greater amounts of switch drain and source metal overlap, which leads to increased switch output capacitance, commonly referred to as “Coss.”
In signal or digital applications, size reduction is not an impediment to routing. If the application is a power management device, however, the segments of the switch are ideally routed to external pins with very low impedance, and also with the same impedance measured from a common reference point. This condition is difficult to achieve since interior portions of the cells are inherently farther away from the periphery than peripheral portions of the cells, resulting in voltage and power losses in the internal connections to the outside package pins, as reflected by the two challenges described above.
A distributed transmission line problem arises when source, drain, and gate lines are electrically distant from their respective single-point input signal generator. Absent a remedy, electrically long connections become, in effect, delay lines, which cause a problem in turning on or off an unusually large, fine-pitch switch. The effect is a gradual and slow turn-on (or turn-off) behavior that propagates from the input signal generator to an effective current sink from one end of a transmission line to the other end, resulting in portions of the lateral power switch remaining on when other portions have been turned off, or vice versa. This results in a potentially destructive condition for a lateral power switch referred to as “shoot through” since the condition causes a supply rail to short-circuit momentarily to local circuit ground, resulting in a potentially destructive current. Typically such a problem is defeated in circuit design by retarding the speed at which driver circuits turn on or turn off such switches. While this solution is viable, it defeats the purpose of utilizing high-speed LDMOS devices with deep sub-micron, fine-pitch structures. Thus, a high-speed interconnection configuration for large, deep sub-micron switches and a corresponding process for forming such switches would be beneficial.
Accordingly, what is needed in the art is a semiconductor device including switches (e.g., an LDMOS device) and method of forming the same that overcomes switching-speed, layout deficiencies, and switch device structures limitations in the prior art. Additionally, there is a need for a compact LDMOS device that can be switched at high speed and is capable of being used to construct a power converter or portions thereof.